Mate 90: Faster chips without the tools Huawei can't buy

Huawei's new LogicFolding architecture, branded as 'Tau Scaling Law,' addresses the challenge of creating faster chips without access to extreme ultraviolet (EUV) lithography tools. Instead of shrinking transistors further, a method constrained by China's reliance on deep ultraviolet (DUV) lithography, LogicFolding stacks two active circuit layers. This design shortens the distance signals travel between logic blocks by using millions of vertical interconnects, optimizing signal delay.

The Kirin 9050 Pro chip, built with this architecture, reportedly achieves 125 TB/s of inter-die bandwidth and carries 5 million signal bonding points. Huawei claims these innovations result in substantial performance improvements, particularly for sustained workloads where latency reduction is critical. This approach shifts the focus from transistor density, as pursued by Moore's Law, to optimizing signal path and speed.

A key trade-off for LogicFolding is its increased wafer consumption and additional manufacturing steps, which can reduce yield. This concern is amplified by Huawei consumer chief Richard Yu's acknowledgment of limited advanced semiconductor capacity in China, where the company's smartphone chips compete for the same wafer supply as its Ascend AI accelerators. The scalability of LogicFolding beyond a single product line will depend on the growth of China's advanced manufacturing capacity.