China’s CXMT unveils ‘key progress’ on chip structure pursued by Samsung, SK Hynix

CXMT's reported progress centers on a “4F square” design for memory cells. This design allows each cell to occupy an physical area of four square F, where F represents the minimum line width of a semiconductor. This is a reduction from the 6F square-cell structure currently used in mainstream commercial dynamic random-access memory (DRAM).

The core advantage of this smaller cell structure is the ability to achieve higher storage density. By reducing the physical space required for each memory cell, more cells can be integrated onto a single chip. This directly translates to greater data storage capacity within the same physical footprint, which is crucial for modern computing demands.

Beyond density, the development also aims to improve efficiency. While the article does not detail the specific mechanisms for efficiency gains, advancements in transistor design often lead to lower power consumption or faster data access times. These improvements are particularly relevant for server-memory products, where both density and operational efficiency contribute to overall system performance and cost-effectiveness.

The article notes that rivals like Samsung Electronics and SK Hynix are also pursuing similar chip structures. This indicates that the “4F square” approach, or variations of it, represents a significant direction for innovation in the memory chip industry. CXMT's announcement, therefore, positions them as a player making headway in a globally competitive area of semiconductor development.